1. Field of the Invention
This invention relates to instruction encoding and a processor architecture for executing such instructions. The present invention is concerned particularly, but not exclusively, with a processor capable of supporting 3D (three-dimensional) images where the generation of such images is dominated by floating point and multiplication operations.
2. Discussion of the Related Art
Modern multimedia applications place substantial requirements on computing resources. The video gaming industry is of significant commercial value to manufacturers who are constantly striving to develop powerful computing platforms, which provide users with a more exciting interactive experience. The graphics of a video game may be enhanced by creating images that are more life-like. In order for images to be more life-like a video game may require three-dimensional (3D) images and/or the real-time generation of such images. To satisfy these requirements, graphic processors need to perform more operations in a shorter space of time resulting in the need for machines with increased “number-crunching” ability.
One technique for increasing processor performance is using a VLIW (Very Long Instruction Word) format and a processor architecture capable of executing such instructions. VLIW engines are well known, where a fetched VLIW instruction comprises a plurality of operations to be executed simultaneously by different functional units of the VLIW processor.
Although VLIW instructions contain a number of operations to be executed simultaneously, because of instruction dependencies few applications have either sufficient instruction level parallelism (ILP) or the correct mix of instructions to issue every cycle. Therefore, some or all of the operations in a VLIW instruction have to be NOP's (i.e. No Operations). This has the undesirable effect of using up instruction bandwidth and increasing program size.
It is desirable to only fetch and issue instructions that are useful operations. If in a VLIW machine all the functional units were identical then the solution is relatively simple where only a single bit is needed to indicate an end-of-bundle marker. This so-called ‘bundle’ refers to the bundle of instructions contained in a fetched instruction packet. However, for most VLIW engines the functional units are independent and are specific units responsible for executing different operations specified within the instructions of the retrieved bundle. When the functional units are not the same the solution is not so simple, because each instruction in the bundle needs to indicate to which functional unit it is destined, while still providing an indication of the end-of-bundle marker. This requires more bits which may not be available.
One possible solution could be to have a separate packet header or a so-called “bundle header”, which indicates the number of instructions in the bundle and their arrangement. It therefore, becomes possible to eliminate the NOP's, but the bundle header would need to be coded as a byte or half-word resulting in alignment issues for the VLIW instructions.